Bare Die Wafers - Technical Library - Faq's - How Do They Make

Bare Die SMT Distribution At ES Components

ES Components has compiled technical data and statistical information that have been derived from information supplied by manufacturers, distributors and the internet. Although we believe that the information supplied is generally correct, we do not assume any responsibility whatsoever for its accuracy.

	Die Products (View References)
	Introduction To Die Products Unpackaged die allow designers to overcome the challenges of small form factor applications. View
	Known Good Die Known-Good-Die (KGD) processing allows for better yields and improved short-term reliability. View
	Known Good Die Myths Four myths about Known-Good-Die (KGD). View
	Die Case Studies Innovative uses of die products in four different applications. View
	Die Assembly Processes
	System-In-Package Assembly Combining all of the electronic components. View
	Wafer Thinning View
	Die Attach View
	Wire Bond View
	Assembly Process View
	Module Testing View
	Flip-Chip Assembly Offers optimized electrical performance in addition to optimized miniaturization. View
	Solder Flip Chip View
	Underfill Encapsulation View
	Adhesive Flip Chip View
	Wafer Level Packaging View
	Process Flow View
	Process Considerations View
	Chip-On-Board (COB) Assembly Provides the capability to perform direct chip to chip wiring that facilitates improved performance and strong functional integration in many modern high speed applications. View
	Process View
	PCB Preparation View
	Die Attach View
	Encapsulation View
	More Encapsulation View
	Challenges In Bare Die Mounting Challenges In Bare Die Mounting (Larry Gilg Die Products Consortium Austin,Texas) View

	Quality & Reliability
	Guidelines For Handling Die General Guidelines For Handling Die View
	Visual Inspection Criteria Visual criteria for the inspection of unpackaged die and wafers. View
	Contamination View
	Cracks View
	Bridging & Shorting View
	Glassification View
	Scratches View
	Delamination View
	Assembly Workmanship Criteria Criteria covering die placement, encapsulation, spacing, wirebond, and rebonding. View
	Encapsulation View
	Spacing View
	Wirebond View
	Rebonding View
	Chip On Board (COB) Reliability Life test, evaluation systems, process flow design issues. View

	General Guidelines
	Storage, Handling, & Shipping of Die Products Safe handling guidelines for packaged ICs that are practiced in the Surface Mount Technology (SMT) assembly industry, and to provide information to purchasers of wafer and die products. View
	Handling View
	Shipping Materials View
	Shipping Technologies View
	Mounting & Dicing View
	Bare Die Product Standards An overview of Bare Die standards View
	Developing New Standards View
	Existing Standards View
	Articles Useful articles relating to Bare Die technologies.
	Burn-In Effectiveness -- Theory & Measurement View
	Defect Level As A Function Of Fault Coverage View
	Die Products Ideal IC Packaging For Demanding Applications View